Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"RRS cache: a low voltage cache based on timing speculation SRAM with a ..."

Xiaojing Shang et al. (2019)

> Home

Details and statistics

DOI: 10.1145/3357526.3357535

access: closed

type: Conference or Workshop Paper

metadata version: 2020-01-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/memsys/ShangLSSY19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/memsys/ShangLSSY19
Xiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang:
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. MEMSYS 2019: 451-458

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.