"Layout optimizations to decrease internal power and area in digital CMOS ..."

Jordan Innocenti et al. (2015)

Details and statistics

DOI: 10.1109/MIPRO.2015.7160523

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-24

a service of  Schloss Dagstuhl - Leibniz Center for Informatics