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"Design and Analysis of Energy Efficient Reversible Logic based Full Adder."

Jagadeesh Pujar et al. (2019)

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DOI: 10.1109/MWSCAS.2019.8884882

access: closed

type: Conference or Workshop Paper

metadata version: 2022-01-03

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  - https://dblp.org/rec/conf/mwscas/PujarRPHB19
Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B.:
Design and Analysis of Energy Efficient Reversible Logic based Full Adder. MWSCAS 2019: 339-342

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