"A 100MS/s 9-bit Companding SAR ADC with On-Chip Input Driver in 65nm CMOS ..."

Anindya Saha, Saurabh Chaubey, Ramesh Harjani (2018)

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DOI: 10.1109/MWSCAS.2018.8623873

access: closed

type: Conference or Workshop Paper

metadata version: 2019-02-05

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Anindya Saha, Saurabh Chaubey, Ramesh Harjani:
A 100MS/s 9-bit Companding SAR ADC with On-Chip Input Driver in 65nm CMOS for Multi-Carrier Communications. MWSCAS 2018: 174-177

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