"Process/design co-optimization of regular logic tiles for double-gate ..."

Shashikanth Bobba et al. (2012)

> Home

Details and statistics

DOI: 10.1145/2765491.2765503

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

- view
  authority control:
- export record
  dblp key:
  - conf/nanoarch/BobbaGZMSLM12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/nanoarch/BobbaGZMSLM12
Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli:
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. NANOARCH 2012: 55-60

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.