"Parallel Efficient Implementation of Hierarchical Algorithms for Module ..."

Laurence Tianruo Yang (2000)

> Home

Details and statistics

DOI: 10.1109/PCEE.2000.873615

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/parelec/Yang00a
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/parelec/Yang00a
Laurence Tianruo Yang:
Parallel Efficient Implementation of Hierarchical Algorithms for Module Placement of Large Chips. PARELEC 2000: 128-133

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.