"Design of Variable Input Delay Gates for Low Dynamic Power Circuits."

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell (2005)

> Home

Details and statistics

DOI: 10.1007/11556930_45

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/patmos/RajaAB05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/patmos/RajaAB05
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS 2005: 436-445

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.