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"Transistor-Level Gate Modeling for Nano CMOS Circuit Verification ..."

Qin Tang et al. (2010)

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DOI: 10.1007/978-3-642-17752-1_19

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  - conf/patmos/TangZBM10
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Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations. PATMOS 2010: 190-199

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