"HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model - ..."

Fearghal Morgan et al. (2023)

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DOI: 10.1145/3625223.3649280

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Fearghal Morgan, John Patrick Byrne, Abishek Bupathi, Roshan George, Muhammad Adnan Elahi, Frank Callaly, Sean Kelly, Declan O'Loughlin:
HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model - Testbench and EDA Project Generation. RSP 2023: 11:1-11:7

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