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"Power Network Modelling for Hardware in the Loop and Real Time Applications."

Zarko Janda et al. (2018)

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DOI: 10.1109/RTSI.2018.8548451

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

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  dblp key:
  - conf/rtsi/JandaDCD18
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  - https://dblp.org/rec/conf/rtsi/JandaDCD18
Zarko Janda, Jasna Dragosavac, Zoran Ciric, Miroslav Dragicevic:
Power Network Modelling for Hardware in the Loop and Real Time Applications. RTSI 2018: 1-6

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