"Low power, high speed error tolerant multiplier using approximate adders."

Karri Manikantta Reddy et al. (2015)

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DOI: 10.1109/ISVDAT.2015.7208150

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  persistent URL:
  - https://dblp.org/rec/conf/vdat/ReddyNSV15
Karri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha:
Low power, high speed error tolerant multiplier using approximate adders. VDAT 2015: 1-6

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