"A dual-edge sampling CES delay-locked loop based clock and data recovery ..."

Jih Ren Goh, Yen-Long Lee, Soon-Jyh Chang (2015)

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DOI: 10.1109/VLSI-DAT.2015.7114500

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Jih Ren Goh, Yen-Long Lee, Soon-Jyh Chang:
A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. VLSI-DAT 2015: 1-4

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