"On designing two-dimensional scan architecture for test chips."

Yu Huang, Wu-Tung Cheng (2017)

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DOI: 10.1109/VLSI-DAT.2017.7939648

access: closed

type: Conference or Workshop Paper

metadata version: 2019-11-14

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Yu Huang, Wu-Tung Cheng:
On designing two-dimensional scan architecture for test chips. VLSI-DAT 2017: 1-4

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