"Effect of Power Optimizations on Soft Error Rate."

Vijay Degalahal et al. (2003)

> Home

Details and statistics

DOI: 10.1007/0-387-33403-3_1

access: open

type: Conference or Workshop Paper

metadata version: 2018-06-26

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - conf/vlsi/DegalahalRVXI03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/DegalahalRVXI03
Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Effect of Power Optimizations on Soft Error Rate. VLSI-SoC (Selected Papers) 2003: 1-20

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.