"A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration."

Evelina Forno et al. (2018)

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DOI: 10.1109/VLSI-SOC.2018.8644777

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

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Evelina Forno, Andrea Acquaviva, Yuki Kobayashi, Enrico Macii, Gianvito Urgese:
A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration. VLSI-SoC 2018: 31-36

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