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"An easily testable routing architecture of FPGA."

Masahiro Iida et al. (2011)

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DOI: 10.1109/VLSISOC.2011.6081661

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi:
An easily testable routing architecture of FPGA. VLSI-SoC 2011: 106-109

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