"A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs."

Shan Jiang, Manh Anh Do, Kiat Seng Yeo (2006)

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DOI: 10.1109/VLSISOC.2006.313260

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-25

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Shan Jiang, Manh Anh Do, Kiat Seng Yeo:
A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. VLSI-SoC 2006: 352-356

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