"A power-efficient hierarchical network-on-chip topology for stacked 3D ICs."

Debora Matos et al. (2013)

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DOI: 10.1109/VLSI-SOC.2013.6673298

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Debora Matos, Cezar Reinbrecht, Tiago Motta, Altamiro Amadeu Susin:
A power-efficient hierarchical network-on-chip topology for stacked 3D ICs. VLSI-SoC 2013: 308-313

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