"Enabling fast Network-on-Chip topology selection: an FPGA-based runtime ..."

Paolo Meloni, Simone Secchi, Luigi Raffo (2010)

> Home

Details and statistics

DOI: 10.1109/VLSISOC.2010.5642625

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsi/MeloniSR10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/MeloniSR10
Paolo Meloni, Simone Secchi, Luigi Raffo:
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. VLSI-SoC 2010: 43-48

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.