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"Topology synthesis of analog circuits with yield optimization and ..."

Oliver Mitea, Markus Meissner, Lars Hedrich (2011)

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DOI: 10.1109/VLSISOC.2011.6081651

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Oliver Mitea, Markus Meissner, Lars Hedrich:
Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts. VLSI-SoC 2011: 78-81

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