"Methodology for early estimation of hierarchical routing resources in 3D ..."

Krishna Chaitanya Nunna et al. (2012)

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DOI: 10.1109/VLSI-SOC.2012.6379032

access: closed

type: Conference or Workshop Paper

metadata version: 2022-09-06

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Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki J. Murakami:
Methodology for early estimation of hierarchical routing resources in 3D FPGAs. VLSI-SoC 2012: 213-218

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