"Improving the Efficiency of Formal Verification: The Case of Clock-Domain ..."

Guillaume Plassan et al. (2016)

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DOI: 10.1007/978-3-319-67104-8_6

access: closed

type: Conference or Workshop Paper

metadata version: 2017-09-05

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Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione:
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. VLSI-SoC (Selected Papers) 2016: 108-129

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