"High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor."

Senthamaraikannan Raghunath, Syed Mahfuzul Aziz (2006)

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DOI: 10.1109/VLSISOC.2006.313235

access: closed

type: Conference or Workshop Paper

metadata version: 2017-08-28

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Senthamaraikannan Raghunath, Syed Mahfuzul Aziz:
High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor. VLSI-SoC 2006: 210-215

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