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"Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs."
Suleyman Tosun, Hakduran Koc, Nazanin Mansouri (2003)
- Suleyman Tosun, Hakduran Koc, Nazanin Mansouri:

Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs. VLSI 2003: 382-

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