"Automatic netlist scrambling methodology in ASIC design flow to hinder the ..."

Sharareh Zamanzadeh, Ali Jahanian (2013)

> Home

Details and statistics

DOI: 10.1109/VLSI-SOC.2013.6673245

access: closed

type: Conference or Workshop Paper

metadata version: 2017-12-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsi/ZamanzadehJ13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/ZamanzadehJ13
Sharareh Zamanzadeh, Ali Jahanian:
Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering. VLSI-SoC 2013: 52-53

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.