"A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up ..."

Jin-Hyeok Baek et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502299

access: closed

type: Conference or Workshop Paper

metadata version: 2025-10-30

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Jin-Hyeok Baek, Chang-Kyo Lee, Kiho Kim, Daesik Moon, Gil-Hoon Cha, Jin-Seok Heo, Min-Su Ahn, Dong-Ju Kim, Jae-Joon Song, Seokhong Kwon, Jongmin Kim, Kyung-Soo Kim, Jinoh Ahn, Jeong-Sik Nam, Byung-Cheol Kim, Jeong-Hyeon Cho, Jeonghoon Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Ilgweon Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang:
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. VLSI Circuits 2018: 147-148

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