BibTeX record conf/vlsic/ChaeCLCYNHLLSSL19

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@inproceedings{DBLP:conf/vlsic/ChaeCLCYNHLLSSL19,
  author    = {Kwanyeob Chae and
               JongRyun Choi and
               Hyungkwon Lee and
               Jinho Choi and
               Shinyoung Yi and
               Yoonjee Nam and
               Sangyun Hwang and
               Joohyung Lee and
               Won Lee and
               Kihwan Seong and
               Joohee Shin and
               Soo{-}Min Lee and
               Seokkyun Ko and
               Jihun Oh and
               Billy Koo and
               Sanghune Park and
               Jongshin Shin and
               Hyungjong Ko},
  title     = {An 8nm All-Digital 7.3Gb/s/pin {LPDDR5} {PHY} with an Approximate
               Delay Compensation Scheme},
  booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
  pages     = {96},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://doi.org/10.23919/VLSIC.2019.8777959},
  doi       = {10.23919/VLSIC.2019.8777959},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/vlsic/ChaeCLCYNHLLSSL19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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