"A 16nm dual-port SRAM with partial suppressed word-line, dummy read ..."

Yen-Huei Chen et al. (2016)

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DOI: 10.1109/VLSIC.2016.7573459

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang:
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications. VLSI Circuits 2016: 1-2

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