"A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology."

Wei-Zen Chen et al. (2012)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2012.6243765

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/ChenLWJYHLHLL12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/ChenLWJYHLHLL12
Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Guo-Wei Huang, Wen-De Liu, Chih-Hua Hsiao, Shu-Yu Lin, Jung Yen Liao:
A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology. VLSIC 2012: 12-13

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.