"Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital ..."

Chun-Yuan Cheng et al. (2012)

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DOI: 10.1109/VLSIC.2012.6243852

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, Jenn-Shyan Sheu:
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment. VLSIC 2012: 186-187

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