"Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention ..."

Nicky Lu et al. (2021)

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DOI: 10.23919/VLSICIRCUITS52068.2021.9492418

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-02

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Nicky Lu, Chun Shiah, Juang-Ying Chueh, Bor-Doou Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, Chia-Wei Chang, Tzung-Shen Chen:
Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns. VLSI Circuits 2021: 1-2

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