"A clock jitter reduction circuit using gated phase blending between ..."

Kiichi Niitsu et al. (2012)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2012.6243830

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/NiitsuHHOSKYK12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/NiitsuHHOSKYK12
Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi:
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges. VLSIC 2012: 142-143

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.