"An All-Digital True-Random-Number Generator with Integrated De-correlation ..."

Rajesh Pamula et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502375

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-30

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Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe:
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. VLSI Circuits 2018: 1-2

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