Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture ..."

Chun Shiah et al. (2019)

> Home

Details and statistics

DOI: 10.23919/VLSIC.2019.8778049

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/ShiahCCLPCCJCHT19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/ShiahCCLPCCJCHT19
Chun Shiah, C. N. Chang, Richard Crisp, C. P. Lin, C. N. Pan, C. P. Chuang, H. L. Chen, S. H. Jheng, T. F. Chang, W. J. Huang, K. C. Ting, Rick Dai, W. M. Huang, Bor-Doou Rong, Nicky Lu:
A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems. VLSI Circuits 2019: 116-

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.