"A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with ..."

Shinji Tanaka et al. (2014)

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DOI: 10.1109/VLSIC.2014.6858411

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato:
A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. VLSIC 2014: 1-2

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