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"A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz ..."

Li Wang, Zhao Zhang, C. Patrick Yue (2021)

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DOI: 10.23919/VLSICIRCUITS52068.2021.9492377

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-02

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Li Wang, Zhao Zhang, C. Patrick Yue:
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery. VLSI Circuits 2021: 1-2

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