"A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects."

Can Wang et al. (2019)

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DOI: 10.23919/VLSIC.2019.8778159

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-27

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Can Wang, Guang Zhu, Zhao Zhang, C. Patrick Yue:
A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. VLSI Circuits 2019: 274-

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