"A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path ..."

Zhao Zhang, Guang Zhu, C. Patrick Yue (2019)

> Home

Details and statistics

DOI: 10.23919/VLSIC.2019.8778061

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/ZhangZY19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/ZhangZY19
Zhao Zhang, Guang Zhu, C. Patrick Yue:
A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps. VLSI Circuits 2019: 158-

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.