"A New Technique for Leakage Reduction in CMOS Circuits using ..."

Narender Hanchate, Nagarajan Ranganathan (2004)

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DOI: 10.1109/ICVD.2004.1260929

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Narender Hanchate, Nagarajan Ranganathan:
A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. VLSI Design 2004: 228-233

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