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"An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits."
Zbigniew Kalbarczyk et al. (1999)
- Zbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer:

An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. VLSI Design 1999: 260-265

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