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"Temperature and Process Variations Aware Power Gating of Functional Units."

Deepa Kannan et al. (2008)

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DOI: 10.1109/VLSI.2008.83

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/KannanSMBV08
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/KannanSMBV08
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design 2008: 515-520

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