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"Clock Period Minimization with Iterative Binding Based on Stochastic ..."

Vyas Krishnan, Srinivas Katkoori (2008)

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DOI: 10.1109/VLSI.2008.85

access: closed

type: Conference or Workshop Paper

metadata version: 2023-11-12

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/KrishnanK08
Vyas Krishnan, Srinivas Katkoori:
Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis. VLSI Design 2008: 641-646

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