"Optimization of 1.8V I/O circuits for performance, reliability at the ..."

Vinod Menezes et al. (2003)

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DOI: 10.1109/ICVD.2003.1183125

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Vinod Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau:
Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. VLSI Design 2003: 122-127

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