"The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive ..."

Prashant Saxena, Peichen Pan, C. L. Liu (1999)

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DOI: 10.1109/ICVD.1999.745189

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Prashant Saxena, Peichen Pan, C. L. Liu:
The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design 1999: 402-407

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