"A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width ..."

Hongwu Jiang et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830211

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type: Conference or Workshop Paper

metadata version: 2023-03-21

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Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu:
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays. VLSI Technology and Circuits 2022: 266-267

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