"A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based ..."

Chia-Fu Lee et al. (2022)

> Home

Details and statistics

DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830438

access: closed

type: Conference or Workshop Paper

metadata version: 2022-08-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsit/LeeLLMFSCCC22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsit/LeeLLMFSCCC22
Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang:
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. VLSI Technology and Circuits 2022: 24-25

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.