"A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller ..."

Xiaohui Lin, Mohamed Megahed, Tejasvi Anand (2022)

> Home

Details and statistics

DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830355

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-10

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsit/LinMA22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsit/LinMA22
Xiaohui Lin, Mohamed Megahed, Tejasvi Anand:
A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail. VLSI Technology and Circuits 2022: 188-189

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.