"An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique ..."

Weichen Tao et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185415

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type: Conference or Workshop Paper

metadata version: 2023-07-28

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Weichen Tao, Weichen Zhao, Robert Bogdan Staszewski, Fujiang Lin, Yizhe Hu:
An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM. VLSI Technology and Circuits 2023: 1-2

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