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"Architecture and Design Analysis of a Digital Single-Event Transient/Upset ..."

Varadan Savulimedu Veeravalli et al. (2012)

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DOI: 10.1109/DSD.2012.26

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-26

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  dblp key:
  - conf/dsd/VeeravalliPSS12
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  - https://dblp.org/rec/conf/dsd/VeeravalliPSS12
Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid:
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. DSD 2012: 8-17

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