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"A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs."

Vamsi Boppana et al. (1996)

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DOI: 10.1007/3-540-61626-8_109

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-22

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  dblp key:
  - conf/europar/BoppanaSBFL96
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  - https://dblp.org/rec/conf/europar/BoppanaSBFL96
Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu:
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831

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